Modem computer systems may be implemented with several different bus architectures. Two of the more common bus architectures today are PCI and VMEbus. The VMEbus specification is defined in the "VMEbus Specification Manual," which is incorporated herein by reference, as released by the VMEbus International Trade Association. The PCI bus specification is defined in PCI Local Bus Specification, Revision 2.1, which is incorporated herein by reference. The PCI bus specification is available from the PCI Special Interest Group, PO Box 14070, Portland, Oreg. 97214.
PCI is an evolution of the IBM PC/XT/AT architecture and was developed by Intel. PCI stores the most significant byte of a longword at the highest memory address allocated to store that longword, and stores the least significant byte at the lowest memory address. In the art, PCI is called a "little endian" architecture.
VMEbus is an evolution of the Motorola microprocessor architecture and was developed by Motorola, Signetics, Mostek, and Thompson CSF. Many VMEbus devices store the most significant byte of a longword at the lowest memory address, and store the least significant byte at the highest memory address. In the art, VMEbus is called a "big endian" architecture. Thus, the fundamental byte ordering schemes employed by "little endian" and "big endian" architectures differ, and these differences can easily cause problems when PCI and VMEbus must transfer multi-byte data units between themselves.
In more complex data processing systems, PCI systems may be networked with VMEbus systems. Thus, PCI and VMEbus may have to access common resources or transfer data between themselves. A serious compatibility issue arises when words, longwords, or other multi-byte data units must be passed between architectures that store those multi-byte data units differently.
The byte ordering issue surfaces when PCI and VMEbus access a common resource, such as a random access memory (RAM). For example, if PCI writes a longword to an allocated longword memory location in RAM, the most significant byte is stored at the highest memory address. However, if VMEbus attempts to read the longword from the same longword memory location, VMEbus expects the most significant byte to be at the lowest memory address. Thus, the two architectures conflict. Thus, when interfacing a "little endian" architecture, such as PCI, to a "big endian" architecture, such as VMEbus, it is necessary to employ additional circuitry to swap the order of the bytes appropriately as they pass between the architectures.
Adapter circuits such as the "Universe" chip, manufactured by TUNDRA Semiconductor Corporation of Kanata, Ontario, Canada, are available to interface PCI with VMEbus while providing a fixed byte-swapping mode. The Universe chip employs a fixed byte swapping circuit referred to as address invariant, which means that the byte addresses of individual bytes within a multiple byte transfer on PCI are maintained when accessing VMEbus. Thus, the Universe chip maintains the little endian mode even when the bytes are stored on VMEbus memory devices. The Universe chip does not provide a big endian mode whereby the VMEbus memory locations are treated as a big endian architecture. Accordingly, a need exists for a circuit that interfaces PCI to VMEbus while providing sophisticated and flexible byte-swapping capability.
U.S. Pat. No. 5,265,237, issued to Tobias et al., provides a byte-swapping apparatus for use with an AT computer and VMEbus. However, Tobias is somewhat unclear how its control system for enabling and disabling its byte-swapping circuitry operates. Further, Tobias fails to address the problems with byte swapping discussed below.
One shortcoming with existing byte swapping circuits is that they can cause VMEbus timing violations by failing to compensate for the delays inherent in byte-swapping the data bus. The VMEbus specification defines specific signals, called data strobes, that are asserted when the data bus contains stable data during a given bus cycle. On a write cycle, the DS0/DS1 signals serve as the data strobes. On a read cycle, the DTACK signal serves as the data strobe. Any de-stabilization of the data bus while the data strobe signals are asserted is a violation of the VMEbus timing specification.
Since the data path through the byte swapping logic inherently delays the data, the relationship between the data and the VMEbus data strobe signals can become skewed, with the VMEbus data strobe signal being asserted before the bytes are fully swapped. As the byte swapping is completed, the byte swapping circuit must drive the swapped bytes onto the data bus after the VMEbus data strobe signals have been asserted, thus causing a VMEbus timing violation. Accordingly, a need exists for a circuit providing byte-swapping capability while avoiding VMEbus timing violations.
Another problem with existing byte-swapping circuits is that they typically fail to optimize their performance during block transfer bus cycles, such as the BLT instruction defined by the VMEbus specification. As explained further below, the BLT instruction allows for multiple data transfers from successive addresses without the CPU updating the address bus for each transfer. Accordingly, a need exists for a byte-swapping circuit that optimizes its performance during block transfer bus cycles to maximize the throughput of the VMEbus interface.